DocumentCode
2091130
Title
Digital background calibration technique for pipeline ADCs with multi-bit stages
Author
Ginés, Antonio J. ; Peralías, Eduardo J. ; Rueda, Adoración
Author_Institution
Instituto de Microelectonica de Sevilla, Centro Nacional de Microelectron., Sevilla, Spain
fYear
2003
fDate
8-11 Sept. 2003
Firstpage
317
Lastpage
322
Abstract
This paper presents a technique for background calibration of pipeline ADCs with multi-bit stages, based on an adaptive approach. Different implementations of the LMS algorithm have been studied, concluding that the traditional SS-LMS (sign-sign LMS) algorithm has inherent convergence problems in high accuracy ADCs that can be solved considering an SD-LMS (sign-data LMS) implementation.
Keywords
analogue-digital conversion; calibration; circuit simulation; least mean squares methods; network synthesis; SD-LMS algorithm; SS-LMS algorithm convergence; digital background calibration technique; multi-bit stage ADC; pipeline ADC; sign-data LMS; sign-sign LMS; Adaptive arrays; Analog-digital conversion; Calibration; Convergence; Energy consumption; Hardware; Least squares approximation; Pipelines; Radar antennas; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on
Print_ISBN
0-7695-2009-X
Type
conf
DOI
10.1109/SBCCI.2003.1232847
Filename
1232847
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