High-Performance TSV Architecture for 3-D ICs

Author

Daneshtalab, Masoud ; Ebrahimi, Masoumeh ; Liljeberg, Pasi ; Plosila, Juha ; Tenhunen, Hannu

Author_Institution

Dept. of Inf. Technol., Univ. of Turku, Turku, Finland

fYear

2010

fDate

5-7 July 2010

Firstpage

467

Lastpage

468

Abstract

Three-dimensional integrated circuits (3-D ICs) outperform traditional planar ICs in terms of performance, packaging density, interconnection power consumption, and functionality. Since the performance of 3-D ICs employing Through Silicon Vias (TSVs) depends on vertical interlayer interconnects, in this paper we present a high-performance bus architecture for TSVs.

Keywords

integrated circuit interconnections; three-dimensional integrated circuits; 3D IC; high-performance TSV architecture; high-performance bus architecture; three-dimensional integrated circuit; through-silicon-via technology; vertical interlayer interconnects; Computer architecture; Integrated circuit interconnections; Pipeline processing; Synchronization; System-on-a-chip; Three dimensional displays; Topology; Three-dimensional integrated circuits; Through Silicon Vias; pipelined bus;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on

Conference_Location

Lixouri, Kefalonia

Print_ISBN

978-1-4244-7321-2

Type

conf

DOI

10.1109/ISVLSI.2010.24

Filename

5572813

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2091153