DocumentCode
2091177
Title
Integrated circuit EDA design of 10-bit SAR ADC with low power
Author
Bu, Dan ; Wu, Nanjian ; Qiu, Chengjun ; Wang, Junbo
Author_Institution
Key Lab. of Integrated Circuit, Heilongjiang Univ., Harbin, China
fYear
2010
fDate
11-14 Nov. 2010
Firstpage
596
Lastpage
598
Abstract
A 10-bit 1Ms/ps SAR ADC with low power is designed by integrated circuit EDA software, which is realized in a 0.18um CMOS process. The design combines a capacitor DAC, a CMOS dynamic comparator, a SAR digital logic control cell, and a two phase non-overlap clk cell. Through the EDA simulation results, the SAR ADC designed in this paper is suited for low power operation with 30.3 uW from a 1.8V voltage supply, and the input range is rail to rail.
Keywords
CMOS integrated circuits; digital-analogue conversion; electronic design automation; integrated circuit design; low-power electronics; ADC; CMOS process; EDA software; SAR; integrated circuit design; power 30.3 muW; size 0.18 mum; successive approximation register; voltage 1.8 V; Artificial neural networks; CMOS integrated circuits; Integrated circuit modeling; Registers; Semiconductor device modeling; Variable speed drives;
fLanguage
English
Publisher
ieee
Conference_Titel
Communication Technology (ICCT), 2010 12th IEEE International Conference on
Conference_Location
Nanjing
Print_ISBN
978-1-4244-6868-3
Type
conf
DOI
10.1109/ICCT.2010.5688923
Filename
5688923
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