Title :
Memory synthesis for high speed DSP applications
Author :
Lippens, P.E.R. ; Van Meerbergen, J.L. ; van der Werf, A. ; Verhaegh, W.F.J. ; McSweeney, B.T.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
Describes technique for performing automatic memory allocation and address allocation for high-speed applications. Memory access conflicts are solved and a global strategy to merge memory units is presented. Efficient reuse of memory locations is obtained by the proposed address allocation techniques. The techniques are based on a stream model for describing data transport. As a specific application, the memory management of the PHIDEO silicon compiler is discussed
Keywords :
computerised signal processing; memory architecture; storage management; PHIDEO silicon compiler; access conflicts; address allocation; automatic memory allocation; data transport; global strategy; high speed DSP applications; memory locations; memory management; stream model; Arithmetic; Bandwidth; Delay; Digital signal processing; High level synthesis; Laboratories; Memory management; Network synthesis; Random access memory; Streaming media;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164138
