DocumentCode
2091286
Title
Cycle time learning curve in semiconductor foundry industry
Author
Chien, Cheng Chung ; Meng, Cheng ; Chen, Kuo Lien ; Hung, Kuo Tung
Author_Institution
TSMC, Hsinchu
fYear
2005
fDate
13-15 Sept. 2005
Firstpage
359
Lastpage
360
Abstract
Faster cycle time is considered to be one of the key factors for the competitive semiconductor foundry industry. During the past decades, many studies had tried to provide rules and models to guide activities for reduction of cycle time. [Yu Hsin Lin et al.] [Wallace J. Hopp et al.] Most of studies aimed on Issue of WIP/tool/dispatch and line balance to reach a cycle time target. But, what´s a good cycle time target? How to set a good cycle time target? Learning curve provide us a good way to answer these questions and show us how powerful it is. In this paper, we establish cycle time road map by applying learning curve approach [Benjamin W. Niebel] to find an empirical rule. Based on this rule, we can define cycle time goal, road map, and long-term activities to make the most profits for the company. We collected historic data and used regression function to find the learning rate. Using the rate we set a tough but reasonable target to drive C/T reduction activities to have a most competitive cycle time
Keywords
foundries; integrated circuit manufacture; lead time reduction; regression analysis; work in progress; cycle time learning curve; cycle time reduction; cycle time road map; cycle time target; line balance; regression function; semiconductor foundry industry; Foundries; Production; Roads;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7803-9143-8
Type
conf
DOI
10.1109/ISSM.2005.1513377
Filename
1513377
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