A novel three dimensional BiCMOS process using epitaxial lateral overgrowth of silicon

Author

Bashir, R. ; Venkatesan, S. ; Neudeck, G.W.

Author_Institution

Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

1991

fDate

12-15 May 1991

Abstract

A 12-mask novel BiCMOS process, incorporating a vertically integrated three-dimensional CMOS inherently merged with a high-performance bipolar transistor is presented. The BiCMOS process uses selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) to form the active device regions. The features of the process are described, and key issues are addressed through simulation and preliminary experimental results. Two-dimensional SUPREM4 simulations indicate that shallow junctions can be obtained in the bipolar as well as the CMOS. Some scanning electron micrographs are presented in support of the feasibility of the process

Keywords

BIMOS integrated circuits; epitaxial growth; integrated circuit technology; silicon; 2D simulations; 3D process; ELO; SUPREM4 simulations; Si; epitaxial lateral overgrowth; scanning electron micrographs; selective epitaxial growth; shallow junctions; three dimensional BiCMOS process; twelve mask process; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Delay effects; Energy consumption; Impedance; MOSFET circuits; Silicon; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164140

Filename

164140