DocumentCode
2091372
Title
Dynamic Power Management on LDPC Decoders
Author
Amador, Erick ; Knopp, Raymond ; Rezard, Vincent ; Pacalet, Renaud
Author_Institution
EURECOM, Sophia Antipolis, France
fYear
2010
fDate
5-7 July 2010
Firstpage
416
Lastpage
421
Abstract
This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitoring of a convergence metric independent from the message computation kernel. Furthermore we analyze the feasibility of a VLSI implementation for such algorithm. Up to 54% savings in energy were achieved with a relatively low loss on error-correcting performance.
Keywords
VLSI; iterative decoding; parity check codes; LDPC decoders; VLSI implementation; dynamic power management; iterative decoding; low density parity check code; online algorithm; power manageable decoder; Convergence; Decoding; Estimation; Iterative decoding; Measurement; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on
Conference_Location
Lixouri, Kefalonia
Print_ISBN
978-1-4244-7321-2
Type
conf
DOI
10.1109/ISVLSI.2010.70
Filename
5572822
Link To Document