DocumentCode
2091408
Title
Dual (n/sup +p/sup +/) polycide gate technology using Si-rich WSi/sub x/ to exterminate lateral dopant diffusion
Author
Fujii, T. ; Hashimoto, S. ; Hori, T.
Author_Institution
Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan
fYear
1994
fDate
7-9 June 1994
Firstpage
117
Lastpage
118
Abstract
We have developed a new technology to solve the device degradation of the dual-polycide-gate N/sup +P/sup +/ CMOS due to the lateral dopant diffusion in the silicide. This was realized by using a Si-rich WSi/sub x/ without any other process steps. With this technology, no significant threshold voltage shift was observed in PMOS even after 900/spl deg/C annealing. This is because the grain growth of the excess Si in the WSi/sub x/ blocks the lateral dopant diffusion path.<>
Keywords
CMOS integrated circuits; annealing; grain growth; metallisation; tungsten compounds; 900 degC; CMOS; Si-rich WSi/sub x/; WSi/sub 2/; annealing; device degradation; dual n/sup +p/sup +/ polycide gate technology; grain growth; lateral dopant diffusion; threshold voltage shift; Annealing; CMOS technology; Crystallization; Fabrication; Grain boundaries; Paper technology; Semiconductor process modeling; Silicides; Threshold voltage; X-ray scattering;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-1921-4
Type
conf
DOI
10.1109/VLSIT.1994.324429
Filename
324429
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