Robustness evaluation of cost-optimum sampling plan for in-line wafer inspection by using Taguchi methods

Author

Suzuki, Ryo ; Nakamae, Koji ; Fujioka, Hiromu

Author_Institution

Fukui Technol. Univ., Japan

fYear

2005

fDate

13-15 Sept. 2005

Firstpage

386

Lastpage

389

Abstract

The robustness of the cost-optimum sampling plan is evaluated by using the robustness evaluation procedure based on Taguchi methods. The procedure is a four-step approach: (1) design, (2) measurement, (3)SN analysis, and (4) analysis of variance (ANOVA) as to the result with the highest SN ratio. The contribution of each factor and the interaction between various factors of an experiment can be quantitatively determined by using ANOVA. Simulation study shows that the cost optimum combination of sampling plan and threshold gives the maximum robustness against many process fluctuations. When improving the noise factor with high contribution, the profit is increased by about 20%.

Keywords

Taguchi methods; costing; design; inspection; integrated circuit manufacture; sampling methods; SN ratio; Taguchi methods; analysis of variance; cost-optimum sampling plan; inline wafer inspection; noise factor; robustness evaluation; Analysis of variance; Analytical models; Discrete event simulation; Fabrication; Fluctuations; Inspection; Random access memory; Robustness; Sampling methods; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on

Print_ISBN

0-7803-9143-8

Type

conf

DOI

10.1109/ISSM.2005.1513385

Filename

1513385