Rule Pattern Parallelization of Packet Filters on Muti-core Environments

Packet filters are essential for most types of recent information network technologies. To achieve packet filters with high performance, flexibility, and cost-efficiency, the performance must be improved through multi-core processing and single instruction multiple data (SIMD) operations for software-based solutions on general-purpose CPUs. In this work, rule pattern parallelization for latency intensive filtering is investigated. Two types of rule pattern parallelization (range parallelization and modulo parallelization) are introduced and a performance model is analytically derived. Packet filter programs are implemented using range parallelization, modulo parallelization, and a hybrid of the two on two different hardware environments, i.e., the Cell and the Xeon cores. The experimental results validate the analytical model and show the baseline performance, which demonstrates the considerable potential of the rule pattern parallelization approach.