DocumentCode
2091719
Title
Extraction of process-induced damage in low-k/Cu damascene structure
Author
Chikaki, S. ; Shimoyama, M. ; Yagi, R. ; Yoshino, T. ; Shishida, Y. ; Ono, T. ; Ishikawa, A. ; Fujii, N. ; Nakayama, T. ; Kohmura, K. ; Tanaka, H. ; Kawahara, J. ; Matsuo, H. ; Takada, S. ; Yamanishi, T. ; Hishiya, S. ; Hata, N. ; Kinoshita, K. ; Kikkawa,
Author_Institution
MIRAI, Assoc. of Super-Adv. Electron. Technol., Ibaraki, Japan
fYear
2005
fDate
13-15 Sept. 2005
Firstpage
422
Lastpage
425
Abstract
This paper describes the extraction of process-induced damage in low-k/Cu damascene by comparing measured data of interline capacitances of Cu interconnects and parasitic capacitances between the line and the substrate with simulation results. The effective dielectric constants were extracted by fitting the simulated results to the measured capacitances. The extracted dielectric constant of the low-k film increased from 2.1 to 4.5 with decreasing the spacing from 800 nm to 140 nm, indicating that the interfacial damage was induced between low-k and cap layer. It is shown that the interfacial damaged layer with a thickness of 10 nm and a k-value of 34.5 could be formed due to wet chemicals during CMP or Cu electrochemical plating or wet cleaning. The simulated interlines capacitance fitted well to measured data, assuming the void-like damage in the low-k film. Lateral sidewall damage could be caused by dry etching and ashing.
Keywords
capacitance measurement; chemical mechanical polishing; dielectric thin films; etching; finite element analysis; integrated circuit interconnections; integrated circuit manufacture; permittivity; 10 nm; 800 to 140 nm; Cu; cap layer; damascene structure; dielectric constant; dry etching; electrochemical plating; interline capacitances; low-k film; parasitic capacitances; process-induced damage; void-like damage; wet cleaning; Capacitance measurement; Cleaning; Data mining; Dielectric constant; Dielectric measurements; Electrodes; Impedance; Integrated circuit interconnections; Parasitic capacitance; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on
Print_ISBN
0-7803-9143-8
Type
conf
DOI
10.1109/ISSM.2005.1513395
Filename
1513395
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