DocumentCode
2091764
Title
Experimental 2.0 V power/performance optimization of a 3.6 V-design CMOS microprocessor-PowerPC 601
Author
Bertsch, J. ; Bernstein, K. ; Heller, L. ; Nowak, E. ; White, F.
Author_Institution
IBM Microelectron., Essex Junction, VT, USA
fYear
1994
fDate
7-9 June 1994
Firstpage
83
Lastpage
84
Abstract
An experimental 2.0 V PowerPC 601 microprocessor demonstrating 3/spl times/ active power reduction and performance comparable to the 3.6 V version has been fabricated. The standard 3.6 V 0.6 /spl mu/m CMOS technology was modified for low-power operation with unmodified circuits/masks. No degradation to yield was observed. Experimental low-voltage PowerPC 601 process/device alterations and test results are described.<>
Keywords
CMOS integrated circuits; microprocessor chips; 0.6 micron; 2 V; CMOS microprocessor; PowerPC 601; low-power operation; power/performance optimization; CMOS technology; Capacitance; Circuit testing; Degradation; Implants; Microelectronics; Microprocessors; Optimization; Paper technology; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-1921-4
Type
conf
DOI
10.1109/VLSIT.1994.324444
Filename
324444
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