Switch-level timing models in the MOS simulator BRASIL

New timing models have been developed and implemented in the switch-level timing simulator BRASIL which are able to give fairly accurate signal waveforms. This enables the detection of faulty aspect ratios, dynamic hazards and races and timing faults caused by clock skew in NMOS and CMOS circuits. In contrast to most existing switch-level timing simulators the algorithm is not restricted to tree structures of the active subnetworks