DocumentCode
2092679
Title
Generic global placement and floorplanning
Author
Eisenmann, Hans ; Johannes, Frank M.
Author_Institution
Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
fYear
1998
fDate
19-19 June 1998
Firstpage
269
Lastpage
274
Abstract
We present a new force directed method for global placement. Besides the well-known wire length dependent forces we use additional forces to reduce cell overlaps and to consider the placement area. Compared to existing approaches, the main advantage is that the algorithm provides increased flexibility and enables a variety of demanding applications. Our algorithm is capable of addressing the problems of global placement, floorplanning, timing minimization and interaction to logic synthesis. Among the considered objective functions are area, timing, congestion and heat distribution. The iterative nature of the algorithm assures that timing requirements are precisely met. While showing similar CPU time requirements it outperforms Gordian by an average of 6 percent and TimberWolf by an average of 8 percent in wire length and yields significantly better timing results.
Keywords
VLSI; circuit layout CAD; minimisation; timing; area; cell overlaps; congestion; floorplanning; force directed method; generic global placement; heat distribution; logic synthesis; timing; timing minimization; Central Processing Unit; Circuits; Electronic design automation and methodology; Iterative algorithms; Logic; Minimization methods; Partitioning algorithms; Permission; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1998. Proceedings
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-89791-964-5
Type
conf
Filename
724480
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