Design of a Partially Buffered Crossbar Router for Mesh-Based Network-on-Chips

With an increase in the number of transistors on-chip, the complexity of the system also increases. In order to cope with the growing interconnection infrastructure, the Networks-on-chip (NoC) concept was introduced. The router plays an important role since it can affect the overall performance of the NoC. In the literature, the NoC employs input-queued routers to receive and transmit packets. In this study, we employ a Partially Buffered Crossbar (PBC) router architecture which consists of virtual channels (VCs) and a small number of separate internal buffers that are maintained per fabric column output for the NoC. In our experiment, results show that the performance of a PBC router can improve a lot compared with a traditional virtual channel (TVC) router.