Injection locked phase lock loop clock recovery circuit at 1.25 Gb/s

Future local area distribution networks will require optical interconnects between various processors or video distribution nodes, which operate in excess of gigabit per second (Gb/s) with very low prime power consumption. The practical limitation of the receiver is unavailability of low power consuming clock recovery circuits. To overcome this limitation, we present a new design method for low power consuming optical receiver/clock recovery circuit, by extracting the clock signal from ECL compatible data streams above Gb/s, and regenerating the original data signal.