Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis

It is well understood that frequency independent lumped-element circuits can be used to accurately model proximity and skin effects in transmission lines. Furthermore, it is also understood that these circuits can be synthesized knowing only the high and the low frequency resistances and inductances. Existing VLSI extraction tools however, are not efficient enough to solve for the frequency dependent resistances and inductances on large VLSI layouts, nor do they synthesize circuits suitable for timing analysis. We propose a rules-based method that efficiently and accurately captures the high and low frequency characteristics directly from layout shapes, and subsequently synthesizes a simple frequency independent ladder circuit suitable for timing analysis. We compare our results to other simulation results.