DocumentCode :
2094602
Title :
Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology
Author :
Yeh, Jen-Chieh ; Ji, Kung-Ming ; Tung, Shing-Wu ; Tseng, Shau-Yin
Author_Institution :
Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
fYear :
2011
fDate :
2-4 Sept. 2011
Firstpage :
851
Lastpage :
856
Abstract :
The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a multi-core computing platform which consists of general-purpose microprocessor and dual programmable digital signal processor (DSP) cores for multimedia applications. To demonstrate its outstanding performance and energy efficiency, we develop multimedia and image processing applications, such as H.264 decoding and object detection, on this multi-core computing platform. In addition, to evaluate the system performance and energy efficiency, electronic system-level (ESL) design with power information is conducted for the embedded system evaluation. According to the experimental results, the system-level virtual platform can assist the hardware engineers and software engineers to enhance the multi-core platform performance and application efficiency, respectively. The system-level design methodology benefits to the embedded multi-core design are discussed.
Keywords :
computational complexity; digital signal processing chips; embedded systems; image coding; multimedia computing; multiprocessing systems; system-on-chip; DSP; ESL; H.264 decoding; computational complexity; digital signal processor; electronic system level; embedded system evaluation; hardware engineers; higher communication bandwidth; image processing applications; multicore SoC implementation; multicore computing platform; multicore integration; multimedia applications; object detection; power information; software engineers; system level design methodology; Algorithm design and analysis; Decoding; Digital signal processing; Multimedia communication; Software; System performance; System-on-a-chip; DSP; Electronic System-Level (ESL); Multi-core SoC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computing and Communications (HPCC), 2011 IEEE 13th International Conference on
Conference_Location :
Banff, AB
Print_ISBN :
978-1-4577-1564-8
Electronic_ISBN :
978-0-7695-4538-7
Type :
conf
DOI :
10.1109/HPCC.2011.121
Filename :
6063087
Link To Document :
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