Design of a Dual-mode Clock Generator based on a PLL Structure

Author

Zhou Yin ; Wu Xiaobo ; Jiana Lou ; Hu Lin

Author_Institution

Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China

fYear

2010

fDate

28-31 March 2010

Firstpage

1

Lastpage

3

Abstract

A Dual-mode clock generator based on a PLL(phase locked Loop)was proposed. The circuit, which provides 400 KHz internal fixed frequency mode and external input mode with a phase-lockable frequency range from 400 KHz to 2 MHz, is applicable to SMPS (Switching Mode Power Supply) controller IC to optimize its performance. A novel oscillation generator for low frequency application is introduced. The circuit was designed under 1.5 um BCD (Bipolar-CMOS-DMOS) process technology. The simulation results show the circuit works well and achieves all expected functions.

Keywords

CMOS integrated circuits; phase locked loops; switched mode power supplies; PLL structure; SMPS; bipolar-CMOS-DMOS process; dual-mode clock generator; frequency 400 kHz; frequency 400 kHz to 2 MHz; low frequency application; oscillation generator; phase locked Loop; size 1.5 micron; switching mode power supply; Circuit simulation; Clocks; Phase detection; Phase frequency detector; Phase locked loops; Power system management; Signal generators; Switched-mode power supply; Very large scale integration; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Power and Energy Engineering Conference (APPEEC), 2010 Asia-Pacific

Conference_Location

Chengdu

Print_ISBN

978-1-4244-4812-8

Electronic_ISBN

978-1-4244-4813-5

Type

conf

DOI

10.1109/APPEEC.2010.5448494

Filename

5448494