• DocumentCode
    2095203
  • Title

    Non-destructive inverse modeling of copper interconnect structure for 90nm technology node

  • Author

    Kunikiyo, T. ; Watanabe, T. ; Kanamoto, T. ; Asazato, H. ; Shirota, M. ; Eikyu, K. ; Ajioka, Y. ; Makino, H. ; Ishikawa, K. ; Iwade, S. ; Inoue, Y. ; Yamashita, K. ; Kobayashi, M. ; Gohda, A. ; Oda, Y. ; Yamaguchi, R. ; Umimoto, H. ; Ohtani, K.

  • Author_Institution
    Renesas Technol. Corp., Hyogo, Japan
  • fYear
    2003
  • fDate
    3-5 Sept. 2003
  • Firstpage
    31
  • Lastpage
    34
  • Abstract
    We propose non-destructive inverse modeling of copper interconnect cross-sectional structures, which reproduces the pitch dependence of intraand interlayer coupling capacitance parasitic to the interconnect. The coupling capacitances, as well as fringing capacitance, are measured by a proposed test structure based on the charge-based capacitance measurement (CBCM) method (J. C. Chen et al., Tech. Dig. of IEDM, p.69-72, 1996). The present methodology not only provides accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlayer dielectric (ILD) thickness and interconnect drawn width reduction or swelling for process control as well. It also ensures the accuracy of LPE (layout parameters extraction) for the 90 nm technology node and beyond.
  • Keywords
    capacitance measurement; copper; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; semiconductor process modelling; 90 nm; CBCM method; Cu; ILD thickness; LPE; capacitance variation; charge-based capacitance measurement method; copper interconnect cross-sectional structures; fringing capacitance; interconnect drawn width reduction; interconnect swelling; interlayer coupling capacitance; interlayer dielectric thickness variability; intralayer coupling capacitance; layout parameters extraction; nondestructive inverse modeling; parasitic capacitance; pitch dependent coupling capacitance; process control; Capacitance measurement; Copper; Current measurement; Dielectric measurements; Feedback; Inverse problems; Parameter extraction; Parasitic capacitance; Process control; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on
  • Conference_Location
    Boston, MA, USA
  • Print_ISBN
    0-7803-7826-1
  • Type

    conf

  • DOI
    10.1109/SISPAD.2003.1233630
  • Filename
    1233630