DocumentCode :
2095349
Title :
Fully testable PLA design with minimal extra input
Author :
Chiou, Che W. ; Yang, Ted C.
Author_Institution :
Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear :
1990
fDate :
12-15 Mar 1990
Firstpage :
633
Lastpage :
638
Abstract :
Due to its popular application in the design of LSI/VLSI circuits, testable PLAs have become an important topic. Bozorgui-Nesbat and McCluskey (1986) offered a low-overhead method which adds extra inputs rather than shift registers to design a fully testable PLA. However, to design such a PLA with a minimal number of extra inputs is an NP complete problem. A rule to modify an arbitrary irredundant PLA which needs fewer extra inputs than other existing methods to make the modified PLA fully testable is presented. It covers multiple stuck-at faults, multiple extra devices, and multiple missing devices, except multiple redundant extra devices in the OR plane of a PLA. In addition, the aforementioned problem is shown no longer NP complete for the modified PLA
Keywords :
computational complexity; logic arrays; logic testing; LSI/VLSI; NP complete problem; OR plane; fully testable PLA design; minimal extra input; multiple extra devices; multiple missing devices; multiple stuck-at faults; Application software; Circuit testing; Decoding; Design engineering; Design methodology; Large scale integration; Logic testing; Programmable logic arrays; Shift registers; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
Type :
conf
DOI :
10.1109/EDAC.1990.136723
Filename :
136723
Link To Document :
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