Title :
Optimization of sub-50 nm MOSFETs to mitigate drive current degradation due to silicon recess in S/D
Author :
Shiho, Yasuhito ; Winstead, Brian ; Foisy, Mark ; Orlowski, Marius
Author_Institution :
Motorola DigitaI DNA Labs., Austin, TX, USA
Abstract :
The recess of silicon in the source/drain and extension area severely compromises the performance of sub-50 nm MOSFETs. In this paper we investigate the influence of silicon recess on the transistor characteristics using process and device simulation, and systematically map the engineering space for optimization of channel, halo, S/D implants, spacer formations, silicidation and integration schemes to mitigate the silicon surface gouging using response surface modeling.
Keywords :
MOSFET; elemental semiconductors; optimisation; semiconductor device models; silicon; 50 nm; Si; Si recess in S/D; channel; engineering space; extension area; halo; integration schemes; mitigate drive current degradation; optimization; process and device simulation; response surface modeling; silicidation; source/drain area; spacer formations; sub-50 nm MOSFETs; transistor characteristics; Capacitance; Current density; Degradation; Doping profiles; Implants; MOSFETs; Response surface methodology; Semiconductor device modeling; Silicides; Silicon;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on
Conference_Location :
Boston, MA, USA
Print_ISBN :
0-7803-7826-1
DOI :
10.1109/SISPAD.2003.1233668
