Compact modeling of flash memory cells including substrate-bias-dependent hot-electron gate current

Author

Sonoda, Ken´ichiro ; Tanizawa, Motoaki ; Shimizu, Satoshi ; Araki, Yasuhiko ; Kawai, Shinji ; Ogura, Taku ; Kobayashi, Shin Ichi ; Ishikawa, Kiyoshi ; Inoui, Y. ; Kotani, Norihiko

Author_Institution

LSI Manuf. Technol. Unit, Renesas Technol. Corp, Hyogo, Japan

fYear

2003

fDate

3-5 Sept. 2003

Firstpage

215

Lastpage

218

Abstract

We propose a compact model for flash memory cells that is suitable for SPICE simulation. The model includes a hot-electron gate current model that considers not only Channel Hot Electron (CHE) injection but also CHannel Initiated Secondary ELectron (CHISEL) injection to express properly substrate bias dependence. Simulation results of both programming and erasing characteristics for 130 nm-technology flash memory cells indicate that our model is useful in designing and optimizing circuit for flash memories.

Keywords

SPICE; flash memories; hot carriers; impact ionisation; optimisation; semiconductor device models; Channel Hot Electron injection; SPICE simulation; channel initiated secondary electron injection; compact modeling; flash memory cells; hot-electron gate current model; substrate-bias-dependent hot-electron gate current; Channel hot electron injection; Circuit simulation; Circuit synthesis; Design optimization; Energy consumption; Flash memory; Flash memory cells; MOSFET circuits; Nonvolatile memory; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on

Conference_Location

Boston, MA, USA

Print_ISBN

0-7803-7826-1

Type

conf

DOI

10.1109/SISPAD.2003.1233675

Filename

1233675