DocumentCode
2096467
Title
Physical compact model for threshold voltage in short-channel double-gate devices
Author
Kim, Keunwoo ; Fossum, Jerry G. ; Chuang, Ching-Te
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2003
fDate
3-5 Sept. 2003
Firstpage
223
Lastpage
226
Abstract
Compact physics/process-based model for threshold voltage in double-gate devices is presented. Drain-induced barrier lowering and short-channel-induced barrier lowering models for double-gate and bulk-Si devices are derived. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled (L/sub eff/=25 nm) double-gate and bulk-Si devices.
Keywords
MOSFET; semiconductor device models; 25 nm; physical compact model; predictability; short-channel double-gate devices; threshold voltage; validity; Back; Capacitance; Current-voltage characteristics; Extrapolation; Intrusion detection; MOSFET circuits; Photonic band gap; Predictive models; Threshold voltage; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on
Conference_Location
Boston, MA, USA
Print_ISBN
0-7803-7826-1
Type
conf
DOI
10.1109/SISPAD.2003.1233677
Filename
1233677
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