Substrate resistance extraction using a multi-domain surface integral formulation

Author

Vithayathil, Anne ; Hu, Xin ; White, Jacob

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

fYear

2003

fDate

3-5 Sept. 2003

Firstpage

323

Lastpage

326

Abstract

In order to assess and optimize layout strategies for minimizing substrate noise, it is necessary to have fast and accurate techniques for computing contact coupling resistances associated with the substrate. In this paper, we describe an extraction method capable of full-chip analysis which combines modest geometric approximations, a novel integral formulation, and an FFT-accelerated preconditioned iterative method.

Keywords

contact resistance; iterative methods; semiconductor device models; semiconductor device noise; surface resistance; FFT-accelerated preconditioned iterative method; computing contact coupling resistances; extraction method; full-chip analysis; geometric approximations; layout strategies; minimizing substrate noise; multi-domain surface integral formulation; substrate resistance extraction; Computer science; Conductivity; Electric potential; Geometry; Integral equations; Iterative methods; Nonhomogeneous media; Slabs; Substrates; Surface resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on

Conference_Location

Boston, MA, USA

Print_ISBN

0-7803-7826-1

Type

conf

DOI

10.1109/SISPAD.2003.1233702

Filename

1233702