Specifications for real-time simulation of switched reluctance drives using microprocessors and FPGAs as computational engines

This paper presents specifications for the real-time simulation of switched reluctance motor (SRM) drives using standard CPUs and FPGAs as computational engines. CPU-based real-time simulation results of a 60-kW current-controlled 6/4 SRM are presented. The SRM is fed by a three-phase unidirectional power converter having three legs, each of which consists of two IGBTs and two free-wheeling diodes. The real-time simulation of the drive is conducted on the RT-LAB real-time simulation platform using Simulink/SimPowerSystems, SRM models and a switching function approach for the inverter. Since the converter is current-controlled, the simulator latency is critical to achieving good accuracy and to avoiding current overshoot. The paper demonstrates that this type of drive can be simulated in real-time at a time-step of 15 mus with good accuracy. A specification is also presented to implement the SRM motor in a FPGA core. An FPGA implementation of the SRM model has the great advantage of very low computational time (estimated at 250 nanoseconds) and minimal total hardware-in-the-loop latency just above 1 microsecond.