Title :
Global routing with crosstalk constraints
Author :
Zhou, Hai ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Abstract :
Due to the scaling down of device geometry and increasing frequency in deep sub-micron designs, crosstalk between interconnection wires has become an important issue in VLSI layout design. In this paper, we consider crosstalk avoidance during global routing. We present a global routing algorithm based on a new Steiner tree formulation and the Lagrangian relaxation technique. We also give theoretical results on the complexity of the problem.
Keywords :
VLSI; circuit layout CAD; crosstalk; integrated circuit interconnections; Steiner tree formulation; VLSI layout; complexity; crosstalk; crosstalk avoidance; device geometry; global routing; interconnection wires; Capacitance; Computational geometry; Crosstalk; Driver circuits; Frequency; Permission; Routing; Very large scale integration; Voltage; Wires;
Conference_Titel :
Design Automation Conference, 1998. Proceedings
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-89791-964-5