In line estimation of the group delay due to pipeline ADCs in mixed signal system

This paper is mainly concerned with the estimation of the group delay in mixed signal system. Pipeline ADCs cause an inherent delay from the input analogue signal to the digitized signal it outputs. This delay is reflected as group delays in frequency domain. This paper presents an inline testing method based on FPGA which requires no external measuring system or device, which contributes to its convenience, flexibility and low cost. Experimental results have confirmed the effectiveness of the measurement method.