A 6-bit low power folding and interpolating ADC

This paper presents a 6-bit high speed, low power CMOS folding and interpolation analog-to-digital converter (ADC). This circuit consists of mainly the folding circuit, zero crossing detectors (ZCD) and a digital encoder. While the folding circuit and ZCD are used to reduce the number of comparators, an encoder is used to convert cyclic thermometer code to binary code. In this paper, the design and simulation of folding and interpolation ADC which utilizes minimum number of comparators is presented. The utilization of folding circuit in the coarse ADC makes it unique. This 6 bit ADC is implemented in CMOS 90nm technology and the performance is measured using transient analysis and fast fourier transform (FFT) analysis.