VHDL Implementation of UART with Status Register

Author

Patel, Naresh ; Patel, Vatsalkumar ; Patel, Vikaskumar

Author_Institution

Sarvajanik Coll. of Eng. & Tech, Surat, India

fYear

2012

fDate

11-13 May 2012

Firstpage

750

Lastpage

754

Abstract

In parallel communication the cost as well as complexity of the system increases due to simultaneous transmission of data bits on multiple wires. Serial communication alleviates this drawback and emerges as effective candidate in many applications for long distance communication as it reduces the signal distortion because of its simple structure. This paper focuses on the VHDL implementation of UART with status register which supports asynchronous serial communication. The paper presents the architecture of UART which indicates, during reception of data, parity error, framing error, overrun error and break error using status register. The whole design is functionally verified using Xilinx ISE Simulator.

Keywords

data communication equipment; hardware description languages; protocols; shift registers; UART; VHDL implementation; Xilinx ISE simulator; asynchronous serial communication; break error using; framing error; long distance communication; overrun error; parallel communication; parity error; signal distortion; status register; universal asynchronous receiver-transmitter; Clocks; Flowcharts; Generators; Receivers; Registers; Simulation; Transmitters; ISE simulator; Universal Asynchronous Receiver Transmitter; VHDL implementation; asynchronous serial communication; status register;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Systems and Network Technologies (CSNT), 2012 International Conference on

Conference_Location

Rajkot

Print_ISBN

978-1-4673-1538-8

Type

conf

DOI

10.1109/CSNT.2012.164

Filename

6200736