Design of UCL hardware filtering system based on FPGA

Author

Ma Jianguo ; Sun Yubo ; Xing Ling ; Ma Qiang

Author_Institution

Sch. of Inf. Eng., Southwest Univ. of Sci. & Technol., Mianyang, China

fYear

2010

fDate

29-31 July 2010

Firstpage

4193

Lastpage

4196

Abstract

UCL (Uniform Content Locator) which can be used in information management and semantic comprehension has attracted more and more attentions from researchers. In this paper, a hardware system of UCL filtering based on FPGA is proposed. In addition a new type of CAM (Content Addressable Memory) and a hardware platform are designed. In experimental environment, the BIP (Broadcasting Internet Protocol) packets formed by indexing UCL in source side are delivered to user terminals, and the filtering system realizes UCL resolving with FPGA in Ethernet. The results show that the system filtering rate is up to 10Mbit/S and maximum frequency reaches 238MHz.

Keywords

Internet; content-addressable storage; field programmable gate arrays; local area networks; protocols; signal processing; Broadcasting Internet Protocol; Ethernet; FPGA; UCL hardware filtering system; content addressable memory; information management; semantic comprehension; system filtering rate; uniform content locator; Clocks; Computer aided manufacturing; Field programmable gate arrays; Filtering; Hardware; Random access memory; Software; CAM; FPGA; Hardware Filtering; UCL;

fLanguage

English

Publisher

ieee

Conference_Titel

Control Conference (CCC), 2010 29th Chinese

Conference_Location

Beijing

Print_ISBN

978-1-4244-6263-6

Type

conf

Filename

5573073