Title :
Using the NS-2 Network Simulator for Evaluating Network on Chips (NoC)
Author :
Ali, Muhammad ; Welzl, Michael ; Adnan, Awais ; Nadeem, Farrukh
Author_Institution :
Inst. of Comput. Sci., Innsbruck Univ.
Abstract :
Networks on chips (NoCs) have been introduced as a remedy for the growing problems of current interconnects in VLSI chips. Being a relatively new domain in research, simulation tools for NoCs are scarce. To fill the gap, we use network simulator NS-2 for simulating NoCs, especially at high level chip design. The huge library of network elements along with its flexibility to accommodate customized designs, NS-2 becomes a viable choice for NoCs. We have used NS-2 to simulate our prototype of a fault tolerant protocol for NoCs
Keywords :
VLSI; circuit simulation; integrated circuit design; network-on-chip; NS-2 network simulator; VLSI chips; fault tolerant protocol; high level chip design; network on chips; Application specific integrated circuits; Computational modeling; Computer networks; Fault tolerance; Libraries; Network-on-a-chip; Object oriented modeling; Protocols; System-on-a-chip; Very large scale integration;
Conference_Titel :
Emerging Technologies, 2006. ICET '06. International Conference on
Conference_Location :
Peshawar
Print_ISBN :
1-4244-0502-5
Electronic_ISBN :
1-4244-0503-3
DOI :
10.1109/ICET.2006.335967
