Pipelining in Embedded Cryptosystems - A Throughput Optimization Approach

The hardware implementations for embedded cryptosystems can be organized using various architectural approaches. These approaches are closely associated with the mode of operation chosen for the algorithm and so affect the overall system throughput and device utilization. This research is aimed towards the characterization of two hardware design architectures, inner round and outer round pipelining in terms of throughput for the hardware implementation of advanced encryption standard (AES) by using counter mode (CTR). Our results show that the system throughput is manifolds better in case of outer round pipelining in comparison to the inner round pipelining for our designs. Further, the device utilization for the two designs substantially differ from one another, whereas, the final report of resources utilized remains the same for both designs