Design and optimization of a low-power and very-high-performance 0.25-μm advanced PNP bipolar process

Author

Djezzar, Boualem

Author_Institution

Centre de Dev. des Technol. Avancees, Algiers, Algeria

Volume

1

fYear

1996

fDate

9-12 Oct 1996

Firstpage

75

Abstract

Low-power and very-high-performance 0.25-μm vertical PNP bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This PNP transistor has a 25-nm-wide emitter, a 38-nm-wide base region, a current gain of 17 (without poly-Si emitter effect), and maximum cut-off frequency of 24-GHz. The conventional ECL circuits, designed by this PNP transistor, exhibit an unloaded gate delay of 22-ps at 1.75-mW, and a delay time less than 16-ps/stage for unloaded ECL ring-oscillator

Keywords

bipolar logic circuits; circuit analysis computing; delays; digital simulation; emitter-coupled logic; logic CAD; very high speed integrated circuits; 0.25 micron; 1.75 mW; 22 ps; 24 GHz; 25 nm; 38 nm; CODECS; ECL circuits; advanced PNP bipolar process; base region; current gain; maximum cut-off frequency; mixed two-dimensional numerical device/circuit simulator; ring-oscillator; unloaded gate delay; CMOS technology; Charge carrier processes; Circuits; Delay effects; Design optimization; Doping; Electron mobility; Laboratories; Microelectronics; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 1996., International

Conference_Location

Sinaia

Print_ISBN

0-7803-3223-7

Type

conf

DOI

10.1109/SMICND.1996.557309

Filename

557309