Title :
Hardware Efficiency Comparison of AES Implementations
Author :
Raneesha, K. ; Vellody, Rema ; Nandakumar, R.
Author_Institution :
Nat. Inst. of Electron. & Inf. Technol., Calicut, India
Abstract :
The AES algorithm can be implemented in different styles at programming levels. The paper compares the hardware efficiency of different AES implementations with respect to their area, speed and power performance especially in two different styles - one using controller and the other one is iterative method. These designs were described using Verilog HDL, simulated using Modelsim® and prototyped in Altera´s platform FPGA.
Keywords :
cryptography; field programmable gate arrays; hardware description languages; AES algorithm; Altera´s platform FPGA; Modelsim; Verilog HDL; hardware description languages; hardware efficiency comparison; iterative method; Encryption; Field programmable gate arrays; Hardware; Iterative methods; Power dissipation; Thermal analysis; AES; FPGA; Rijndael; VLSI Cryptosystems; hardware efficiency; power analysis;
Conference_Titel :
Communication Systems and Network Technologies (CSNT), 2012 International Conference on
Conference_Location :
Rajkot
Print_ISBN :
978-1-4673-1538-8
DOI :
10.1109/CSNT.2012.187
