DocumentCode
2098526
Title
Practical experiences with standard-cell based datapath design tools. Do we really need regular layouts?
Author
Ienne, Paolo ; Griessing, Alexander
Author_Institution
Siemens AG, Munich, Germany
fYear
1998
fDate
19-19 June 1998
Firstpage
396
Lastpage
401
Abstract
Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test circuits. Algorithmic generation of netlists and of relative cell placement can help reducing area but, contrary to common belief appears often detrimental to speed. Extraction of regularity from synthesized netlists is difficult and requires counterproductive simplifications to the synthesis process. Most promising are synthesis tools which can generate placement data; yet, no tool of this class appears ready today.
Keywords
circuit layout CAD; high level synthesis; logic CAD; datapath design; design flows; placement data; synthesis tools; synthesized netlists; test circuits; tools; Adders; Circuit synthesis; Circuit testing; Data mining; Logic arrays; Logic circuits; Multiplexing; Permission; Signal processing; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1998. Proceedings
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-89791-964-5
Type
conf
Filename
724505
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