Title :
A 4Gbps clock and data recovery circuit and its bit error rate estimation
Author_Institution :
STMicroelectronics, Noida, India
Abstract :
This paper describes a reference-less 4 Gbps Clock and Data Recovery (CDR) circuit. A novel compensation technique is used to initialize the Voltage Controlled Oscillator´s (VCO) frequency close to the data rate. A new method for the theoretical estimation of filtered phase noise power responsible for bit error is presented and is verified experimentally. CDR is implemented in 65 nm CMOS technology on 1.8 V supply and consumes 50 mA current.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; correlation methods; error compensation; error statistics; estimation theory; phase noise; voltage-controlled oscillators; CMOS technology; VCO frequency; autocorrelation based technique; bit error rate estimation; bit rate 4 Gbit/s; clock-data recovery circuit; compensation technique; current 50 mA; data rate; filtered phase noise power; referenceless CDR circuit; size 65 nm; voltage 1.8 V; voltage controlled oscillator; CMOS integrated circuits; Clocks; Computers; Design automation; Filtering theory; Passive optical networks; Solid modeling;
Conference_Titel :
Communication Technology (ICCT), 2010 12th IEEE International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-6868-3
DOI :
10.1109/ICCT.2010.5689244
