An exact treatment of the achievable closed-loop H2 performance of sampled-data controllers: from continuous-time to open-loop

One of the first design decisions a control engineer must make concerns the capabilities of the real-time feedback processor. Assuming that the controller will be implemented digitally, processor requirements such as computational capability memory, and I/O speed must be determined. To assess these requirements, it is useful to understand how processor capabilities affect the stability and achievable performance of the closed-loop system, including intersample behavior. Although it seems reasonable to conjecture that closed-loop performance improves as processor speed increases, there exist relatively few results that rigorously document this fact. The purpose of this paper is to make significant progress in this direction by means of a control-design procedure that precisely quantifies the dependence of achievable closed-loop performance on sample rate. The goal of this paper is to develop a sampled-data design methodology that accounts precisely for all sampling effects including intersample behavior. A unique feature of the authors´ approach is its unified treatment of both continuous-time and discrete-time controllers. Thus, by appropriate choice of analog-to-digital (A/D) and digital-to-analog (D/A) devices, the authors expect to recover continuous-time controller performance as the sample interval h approaches zero and open-loop performance as h approaches infinity