Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs

Recent significant advancements in FPGAs have made it viable to explore multiprocessor solutions on a single FPGA chip. An efficient communication architecture that matches the needs of the target application is always critical to the overall performance of multiprocessors. Packet-switching network-on-chip (NoC) approaches are being offered to deal with scalability and complexity challenges coming along with the increasing number of processing elements (PEs). Many FPGA-based NoC designs consume significant resources, leaving little room for PEs. We argue that computation is still the primary task of multiprocessors and sufficient resources should be reserved for PEs. This paper presents our novel design and implementation of a resource-efficient communication architecture for multiprocessors on FPGAs. We reduce not only the required number of routers for a given number of PEs by introducing a new PE-router topology, but also resource requirements of each router, while maintaining good performance for typical injection rates.