A Real-Time Embedded System for Stereo Vision Preprocessing Using an FPGA

In this paper a low level vision processing node for use in existing IEEE 1394 camera setups is presented. The processing node is a small embedded system, that utilizes an FPGA to perform stereo vision preprocessing at rates limited by the bandwidth of IEEE 1394a (400 Mbit). The system is used in a hybrid architecture [5], where it produces undistorted and rectified 512 x 512 images at 2 x 15 frames pr. second (fps) as either a downsampled version or a region of interest (ROI) of the high resolution camera output. Three processes are performed: Bayer demosaicing, downsampling and region of interest extraction, and undistortion and rectification. The latency of the system when running at 2 x 15 fps is 30 ms.