DocumentCode
2100640
Title
A reconfigurable logic machine for fast event-driven simulation
Author
Bauer, Jerry ; Bershteyn, Michael ; Kaplan, Ian ; Vyedin, Paul
Author_Institution
Quickturn Design Syst. Inc., San Jose, CA, USA
fYear
1998
fDate
19-19 June 1998
Firstpage
668
Lastpage
671
Abstract
As the density of VLSI circuits increases, software techniques cannot effectively simulate designs through the millions of simulation cycles needed for verification. Emulation can supply the necessary capacity and performance, but emulation is limited to designs that are structural or can be synthesized. The paper discusses a new system architecture that dramatically accelerates event-driven behavioral simulation and describes how it is merged with emulation.
Keywords
VLSI; circuit analysis computing; formal verification; logic CAD; reconfigurable architectures; VLSI circuits; design simulation; emulation; event-driven behavioral simulation; fast event-driven simulation; reconfigurable logic machine; simulation cycles; software techniques; system architecture; verification; Circuit simulation; Circuit synthesis; Computational modeling; Discrete event simulation; Emulation; Field programmable gate arrays; Hardware design languages; Permission; Reconfigurable logic; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1998. Proceedings
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-89791-964-5
Type
conf
Filename
724555
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