A Pulse Width controlled PLL and its automated design flow

This paper presents a Pulse Width controlled PLL which is designed by our customized automated flow. The Pulse Width controlled PLL (PWPLL) structure is a novel time-domain-based analog architecture which claims its small area, power and jitter. It is also compatible with standard-cell based design using a commercial P&R tool. Our design flow automatically synthesizes a circuit netlist, generates its layout and estimates its performance. Not only a final layout but also its post-layout simulation results that confirm its performance are generated only in about one hour. The prototype PWPLL is fabricated in 180nm standard CMOS and it occupies 3970 μm². The frequency range is from 1.35 to 1.6 GHz under a 1.8V supply. The measurement results show that the period jitter is 3.1 ps_rms and the power consumption is 4.0mW at 1.45 GHz.