Title :
Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal Transforms
Author :
Nazario, Rafael A Arce ; Jimenez, M. ; Rodreguez, D.
Author_Institution :
Dept. of Comput. Sci., Univ. of Puerto Rico, San Juan
Abstract :
A well defined target architecture is essential to the success of high-level partitioning and synthesis tools. We present DINAMO, an architectural model tailored for distributed implementations of discrete signal transforms (DSTs) such as FFTs and discrete cosine transforms. DINAMO is a modular generalization of horizontal/vertically folded computational structures, common in fast versions of DSTs. The architecturepsilas systematic definition of functional, communication and control structures, allowed the development of a simplified, equation-based model for obtaining accurate FPGA resource utilization estimates. Resource estimates were obtained with an absolute error of average 7.87% when compared to FPGA synthesis results.
Keywords :
computer architecture; discrete cosine transforms; fast Fourier transforms; field programmable gate arrays; resource allocation; DINAMO; FFT; FPGA synthesis; discrete cosine transforms; discrete signal transforms; distributed hardware implementation; equation-based model; high-level partitioning; synthesis tools; Communication system control; Computer architecture; Control system synthesis; Discrete cosine transforms; Discrete transforms; Equations; Field programmable gate arrays; Flexible printed circuits; Hardware; Signal synthesis; Custom Computing Architectures; Discrete Signal Transforms; FPGA; Resource Estimation;
Conference_Titel :
Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4244-3748-1
Electronic_ISBN :
978-0-7695-3474-9
DOI :
10.1109/ReConFig.2008.70
