A 5–9 GHz CMOS Ultra-wideband power amplifier design using load-pull

The design of 5-9 GHz, two stages CMOS power amplifier (PA) for Ultra-wideband (UWB) is presented in this paper. Post-layout simulation results indicated a power gain S₂₁ of 16± 0.5dB, an input return loss S₁₁ less than -4 dB and an output return loss S₂₂ less than -5 dB over the frequency range of interest. Source-pull contours were used to design the inter stage matching of the PA. The proposed two stages PA achieves an average Power Added Efficiency (PAE) of 12.4% and an output 1-dB compression above 0 dBm over the same frequency band. Moreover, the proposed UWB PA achieves group delay of 170±20 ps with power consumption of 25 mW from a 1.8V supply voltage. The UWB PA is designed in TSMC 0.18 μm CMOS technology.