Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption

The degraded data stability, write ability, and increased leakage power consumption of static random-access memory (SRAM) cells have become primary design concerns with CMOS technology scaling into the sub-22nm channel lengths. A new gate-underlap-engineered eight-transistor SRAM cell is proposed in this paper for stronger data stability, enhanced write ability, and suppressed leakage power consumption in FinFET memory circuits. Gate-underlap lengths of the pull-up and pull-down transistors in cross-coupled inverters of the proposed SRAM cell are elongated and tuned for providing superior electrical characteristics in FinFET memory circuits. With the proposed gate-underlap engineered eight-FinFET SRAM cell, the read static noise margin is enhanced by up to 71.1%, the write voltage margin is increased by up to 29.7%, and the leakage power consumption is reduced by up to 91.8% while maintaining similar layout area as compared to the conventional eight-FinFET SRAM cells in a 15nm FinFET technology.