Low-power design of hybrid digital impedance calibration for process, voltage, temperature compensations

In advanced high-speed communication systems, I/O interfaces require precise impedance matching to maintain signal integrity and avoid signal reflections due to process, voltage, temperature (PVT) variations. This paper presents a power-efficient hybrid digital impedance calibration technique with short calibration time. A high-speed GDDR5 memory I/O is taken as a case study in TSMC 65nm LP technology. In comparison to the conventional binary search algorithm the proposed hybrid algorithm can reduce the calibration time by more than 12% and power by 8.91 mW for the corners close to reference Vdd/2. The impedances are calibrated within +/-2% of target impedance for PFET and +3.3%/-2.8% for NFET.