Embedded memory design using memristor: Retention time versus write energy

Memristor is a good candidate for replacing CMOS-based flash and DRAM due to its superior scalability, low read energy and non-volatility characteristics. Relatively longer write time and high write energy are the main obstacles in the way of adapting memristor for on-chip memory to replace SRAM. The off-to-on resistance ratio for memristor are in excess of 1000x which provides adequate noise margin to separate the on versus off states. In this paper, we explore the design space of memristor by studying retention time, write time, write energy, and noise margin ratio. Our results show that by reducing target retention time both write time and energy can be reduced to a competitive level. In addition, reducing the noise margin reduces both the write time and energy. Our study shows that by reducing retention time to about 4 years write energy can be reduced to 0.1pJ. Compared to SRAM power consumed is 88.6% less for 128KB memory array. Since on-chip memory is not expected to retain data for long time (Jog et al., 2011), our proposed approach can be used in many energy critical applications and is able to reduce system complexity especially power management unit.