DocumentCode
2101216
Title
Dynamically Reconfigurable Split Cache Architecture
Author
Coutinho, Luiza M N ; Mendes, Jose L D ; Martins, Carlos A P S
Author_Institution
Pontifical Catholic Univ. of Minas Gerais
fYear
2008
fDate
3-5 Dec. 2008
Firstpage
163
Lastpage
168
Abstract
Dynamically reconfigurable split cache architecture is a reconfigurable architecture that has all advantages of a split cache and also the ability to reconfigure itself allowing computational performance improvement. Several real traces were performed in order to verify and compare the dynamically reconfigurable split cache architecture and the conventional split cache architecture performance, in most tests the reconfigurable architecture was better than the conventional one.
Keywords
cache storage; formal verification; reconfigurable architectures; computational performance improvement; dynamically reconfigurable split cache architecture; performance verification; Cache memory; Cache storage; Computer architecture; Field programmable gate arrays; High performance computing; History; Memory architecture; Performance evaluation; Reconfigurable architectures; Testing; Cache memories; Computer Architecture; Reconfigurable Computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
Conference_Location
Cancun
Print_ISBN
978-1-4244-3748-1
Electronic_ISBN
978-0-7695-3474-9
Type
conf
DOI
10.1109/ReConFig.2008.46
Filename
4731788
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