DocumentCode :
2101279
Title :
Key Research Issues for Reconfigurable Network-on-Chip
Author :
Dafali, R. ; Diguet, J-Ph ; Sevaux, M.
Author_Institution :
Lab.-STICC dept., Univ. Europeenne de Bretagne, Lorient
fYear :
2008
fDate :
3-5 Dec. 2008
Firstpage :
181
Lastpage :
186
Abstract :
Network on chip (NoC) has emerged as the design paradigm for scalable System on Chip with harsh bandwidth requirements. However, current NoCs remain not flexible enough to support communication dynamic behaviors (size, instances) inherent to a growing majority of embedded systems. Few solutions have been proposed to make NoC reconfigurable using different methods but,to the best of our knowledges, none of them has a clear and reusable design methodology. The first objective of this paper is to propose an overview of existing work as a starting point for research in this domain. Then to deal with the current situation, we introduce a description of a dynamic reconfiguration model for NoC and enumerate several outstanding research issues organized on three topics: dynamic reconfiguration administration, network infrastructure reconfiguration and network protocols reconfiguration.
Keywords :
integrated circuit design; logic design; network-on-chip; dynamic reconfiguration administration; network infrastructure reconfiguration; network protocols reconfiguration; reconfigurable network-on-chip; scalable system on chip; Application software; Communication standards; Design methodology; Embedded system; Field programmable gate arrays; Network-on-a-chip; Open systems; Protocols; Runtime; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4244-3748-1
Electronic_ISBN :
978-0-7695-3474-9
Type :
conf
DOI :
10.1109/ReConFig.2008.72
Filename :
4731791
Link To Document :
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