Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs

In many applications, subsequent tasks differ only in a specific set of parameters. Because of their reconfigurability, FPGAs (field programmable gate arrays) can be configured with an optimized configuration every time these parameter values change. This results in configurations that are smaller and faster than their generic counterparts. Unfortunately, the overhead involved in generating these configurations at run-time with conventional tools is very large. However, if the incoming tasks only differ in a set of parameter values, the use of Tunable LUT (TLUT) circuits can drastically reduce this overhead. A TLUT circuit is a LUT circuit in which the truth tables of the LUTs are expressed as a function of a set of parameters. At run-time the truth tables for a specific set of parameter values can rapidly be calculated by evaluating these functions. Up to now TLUT circuits had to be designed manually resulting in a huge design cost. This paper introduces TMAP2, a software tool based on conventional structural mapping that automatically generates a TLUT circuit starting from an arbitrary Boolean circuit.We have tested TMAP2 on a set of 12 micro-benchmarks and we show a substantial reduction in both the circuits area and maximum depth compared to conventional implementations.